← The wire

Staff Engineer, VLSI Design Engineering (UVM, System Verilog) with 8 to 12 years of experience

Sandisk · Bengaluru, in

Posted 10d ago · first seen by the radar 6d ago · last checked on the employer's board 4d ago

Staff · Onsite · Full-time

This employer's system doesn't publish the description — read it on the application page.

Listing read directly from Sandisk's applicant tracking system. Check frequency varies by source. Listings are removed after successful checks confirm they are no longer present.